This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. section 119 from an application for DEVICE AND METHOD FOR PROCESSING CELL GROUP IN COMMON MEMORY SWITCH filed in the Korean Industrial Property Office on Nov. 11, 1998 and assigned Serial No. 98-48174.
1. Field of the Invention
The present invention relates generally to a common memory switch. In particular, to a cell grouping processing device and method for grouping input/output (I/O) ports.
2. Description of the Related Art
It is known that an exchange system for switching between subscribers is generally provided with a switch. The switch may be embodied in many ways for switching information received through a predetermined input port to a corresponding output port.
Many different types of switches may be used in each exchange system. It would be virtually impossible and of little value to describe all the switch types for exchange systems herein. However, four major design schemes of an asynchronous transfer mode (ATM) switch will be described instead: 1)a shared memory switch; 2)a shared medium switch; 3) a fully interconnected switch; and 4) a space division switch.
Among the aforementioned switches, a common memory switch (or a common buffer switch) is typically used in an ATM exchange system, and its conventional structure is illustrated in FIG. 1.
Referring to FIG. 1, cells are applied to first, second, and third input ports Pin 0, Pin 1, and Pin 2 among four input ports Pin 0 to Pin 3. It is to be assumed that the first, second, and third input ports Pin 0, Pin 1, and Pin 2 are the counterparts of fourth, third, and first output ports Pout 3, Pout 2, and Pout 0, respectively.
In a cell input operation, cells are fed to a multiplexer (MUX) 110 through the corresponding input ports, and the MUX 110 multiplexes the cells into a cell stream. As shown in FIG. 1, for example, the MUX 110 converts the cells received in parallel through the input ports Pin 0 to Pin 3 into a serial cell stream in time division according to the input order and the order of accessing the input ports.
Each cell includes a header for cell routing. This header is extracted from the cell and transmitted to a header converter 140. The extracted header provides information about a destination output port for a corresponding cell. The structure for extracting the header and its operation are a well-known technology and thus their description and illustration is omitted.
The header converter 140 determines whether a cell corresponding to the extracted header is valid or not. Subsequently, an idle address pool (IAP) 170 assigns only a valid cell an available cell address of a common memory 120 in response to a valid check signal RD_IAP received from the header converter 140. In FIG. 1, cell addresses xe2x80x9ca, b, and cxe2x80x9d are assigned to cells having output port designating information xe2x80x9c3, 2, and 0xe2x80x9d, respectively, and the cells output from the MUX 110 are stored at the assigned cell addresses in the common memory 120.
While the header converter 140 stores the cells, it simultaneously checks the output ports through which the stored cells will be transmitted, and generates signals WR0 to WR3 to enable the first to fourth AFIFO (Address First In First Out) buffers 152 to 158, in which the cell addresses will be stored. The AFIFO buffers 152 to 158, which have been enabled by the signals WR0 to WR3, store the cell addresses received from the IAP 170.
An example of the above is when a cell applied to the input port Pin 0 and destined for the output port Pout 3 is assigned a cell address xe2x80x98axe2x80x99 from the IAP 170. The cell address xe2x80x9caxe2x80x9d is stored in the fourth AFIFO buffer 158 enabled by the signal WR3 received from the header converter 140.
During a cell output operation, a read timing generator 180 generates read signals RD0 to RD3 for sequentially reading the cell addresses stored in the first to fourth AFIFO buffers 152 to 158. The read cell addresses are applied to the input of a MUX 160 in different paths. The MUX 160 multiplexes the cell addresses and feeds the multiplexed cell addresses to the common memory 120. xe2x80x9cc, b, and axe2x80x9d are examplarily shown to be fed to the common memory 120 and the common memory 120 outputs the stored cells from the cell addresses xe2x80x9cc, b, and axe2x80x9d in FIG. 1. Here, xe2x80x9cc, b, and axe2x80x9d are arranged in the multiplexed order. In some cases, the common memory 120 reads a vacant AFIFO buffer such as the second AFIFO buffer 154 and then outputs an idle cell. A cell indicated by xe2x80x9cxxxe2x80x9d is an idle cell in FIG. 1.
A demultiplexer (DEMUX) 130 demultiplexes the cells received from the common memory 120 and outputs the demultiplexed cells to their destination output ports.
Meanwhile, the MUX 160 returns the cell addresses to the IAP 170 for the next use as well as feeds them to the common memory 120. An address checker 190 is located in the returning path to determine whether the returned cell addresses have errors, returns only error-free cell addresses to the IAP 170, and discards cell addresses having errors.
As described above, the input ports and the output ports operate individually in the conventional common memory ATM switch. Therefore, once a cell has been applied to a specific input port, it is directed only to an output port being the counterpart of that specific input port. That is, since each address buffer acts individually, a cell applied to each input port at 155 Mbps, for example, is processed only by a switch with a port rate 155 Mbps. For example, if a common memory ATM switch is a 4xc3x974 switch having a cell input rate of 155 Mbps, it cannot operate with use of a 2xc3x972 switch with a cell input rate of 310 Mbps. Thus, constraints are imposed on use of a switch module in designing a system.
It is, therefore, an object of the present invention to provide a common memory switch for enabling group switching and a processing method thereof.
It is another object of the present invention to provide a common memory switch and a processing method thereof, in which an individual port can be used as a grouped port, as well as in an individualized port by utilizing an internal buffer and a buffer manager, in order to increase the efficiency of a switch module.
To achieve the above objects, the present invention provides a device and method for processing a cell group in a common memory switch. Output ports in the common memory switch are divided into an individualized output port group with only one output port as an element, and a grouped output port group with a plurality of output ports as elements, and each output port is assigned to a unique group number. According to an embodiment of the present invention, the cell group processing device includes a multiplexer for multiplexing cells received through input ports. A header converter sequentially receives headers extracted from the multiplexed cells, determines whether the cells are valid, and generates a valid verified signal, and a group signal for a valid cell. An idle address generator sequentially assigns idle addresses at which cells are stored in response to the valid verified signal, and a processor provides the initial grouping information and the initial address buffer select information when a switch module is initialized. A group information memory includes a first table for storing the initial grouping information, and determines grouping information corresponding to the group signal referring to the first table. An address buffer select memory includes a second table for storing the initial address buffer select information, and for then replacing the initial address buffer select information with next address buffer select information upon reception of the next address buffer select information, and determines address buffer select information corresponding to the group signal referring to the second table. An address buffer select information generator receives the grouping information and the address buffer select information, determines the next address buffer select information, and outputs the next address buffer select information to the address buffer select memory. A plurality of address buffers are enabled by the address buffer select information to store idle addresses assigned by the idle address generator, and a common memory stores the cells received from the multiplexer at the idle addresses.